Demonstration of Two-Dimensional Connectivity for a Scalable Error-Corrected Ion-Trap Quantum Processor Architecture

A major hurdle for building a large-scale quantum computer is increasing the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be achieved by moving subregisters consisting of a few ions across the processor. Here, we focus on an architecture...

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Autores: Valentini, M., Van Mourik, M.W., Butt, F., Wahl, J., Dietl, M., Pfeifer, M., Anmasser, F., Colombe, Y., Rössler, C., Holz, P.C., Blatt, R., Bermudez, A., Müller, M., Monz, T., Schindler, P.
Tipo de documento: artigo
Estado:Versão publicada
Data de publicação:2025
País:España
Recursos:Consejo Superior de Investigaciones Científicas (CSIC)
Repositório:DIGITAL.CSIC. Repositorio Institucional del CSIC
OAI Identifier:oai:dnet:digitalcsic_::8d70296d3fc4b225fb472bf09dfe7afa
Acesso em linha:http://hdl.handle.net/10261/427332
https://www.scopus.com/inward/record.uri?eid=2-s2.0-105022605887&doi=10.1103%2Fb9s1-6r44&partnerID=40&md5=c6e2b12aee0dfd56ff0846ff9c731983
Access Level:Acceso aberto
Palavra-chave:Architecture
Computer architecture
Error correction
Quantum channel
Quantum electronics
Quantum noise
Qubits
Array architecture
Coupling rate
Ion traps
Large scale quantum computers
Linear strings
Processor architectures
Quantum processors
Trapped ion
Two-dimensional
Two-dimensional lattices
Trapped ions
id ES_08ce29ec42d707ee3d93b7c7b11bc6cb
oai_identifier_str oai:dnet:digitalcsic_::8d70296d3fc4b225fb472bf09dfe7afa
network_acronym_str ES
network_name_str España
spelling Demonstration of Two-Dimensional Connectivity for a Scalable Error-Corrected Ion-Trap Quantum Processor Architecture Valentini, M. Van Mourik, M.W. Butt, F. Wahl, J. Dietl, M. Pfeifer, M. Anmasser, F. Colombe, Y. Rössler, C. Holz, P.C. Blatt, R. Bermudez, A. Müller, M. Monz, T. Schindler, P. Architecture Computer architecture Error correction Quantum channel Quantum electronics Quantum noise Qubits Array architecture Coupling rate Ion traps Large scale quantum computers Linear strings Processor architectures Quantum processors Trapped ion Two-dimensional Two-dimensional lattices Trapped ions A major hurdle for building a large-scale quantum computer is increasing the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be achieved by moving subregisters consisting of a few ions across the processor. Here, we focus on an architecture, which we refer to as the quantum spring array (QSA), that is based on a rectangular two-dimensional lattice of linear strings of ions. Connectivity between adjacent ion strings can be controlled by adjusting their separation. This requires control of trapping potentials along two directions, one along the axis of the ion string and one radial to it. In this work, we investigate key elements of the QSA architecture along both directions: We show that the coupling rate between neighboring lattice sites increases with the number of ions per site and the motion of the coupled system can be resilient to electrical noise, both being key requisites for fast and high-fidelity quantum gate operations. The coherence of the coupling is assessed and an entangling gate between qubits stored in radially separated trapping regions is demonstrated. Moreover, we demonstrate control over radio-frequency signals to adjust the radial separation, and thus the coupling rate, between strings. We further present constructions for the implementation of parallelized, transversal gate operations, and map the QSA architecture to code primitives for fault-tolerant quantum error correction, providing a step towards a quantum processor architecture that is optimized for large-scale operation. © 2025 authors. Published by the American Physical Society. Published by the American Physical Society under the terms of the "https://creativecommons.org/licenses/by/4.0/"Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI. Peer reviewed American Physical Society http://hdl.handle.net/10261/427332 https://www.scopus.com/inward/record.uri?eid=2-s2.0-105022605887&doi=10.1103%2Fb9s1-6r44&partnerID=40&md5=c6e2b12aee0dfd56ff0846ff9c731983
title Demonstration of Two-Dimensional Connectivity for a Scalable Error-Corrected Ion-Trap Quantum Processor Architecture
spellingShingle Demonstration of Two-Dimensional Connectivity for a Scalable Error-Corrected Ion-Trap Quantum Processor Architecture
Valentini, M.
Architecture
Computer architecture
Error correction
Quantum channel
Quantum electronics
Quantum noise
Qubits
Array architecture
Coupling rate
Ion traps
Large scale quantum computers
Linear strings
Processor architectures
Quantum processors
Trapped ion
Two-dimensional
Two-dimensional lattices
Trapped ions
title_short Demonstration of Two-Dimensional Connectivity for a Scalable Error-Corrected Ion-Trap Quantum Processor Architecture
title_full Demonstration of Two-Dimensional Connectivity for a Scalable Error-Corrected Ion-Trap Quantum Processor Architecture
title_fullStr Demonstration of Two-Dimensional Connectivity for a Scalable Error-Corrected Ion-Trap Quantum Processor Architecture
title_full_unstemmed Demonstration of Two-Dimensional Connectivity for a Scalable Error-Corrected Ion-Trap Quantum Processor Architecture
title_sort Demonstration of Two-Dimensional Connectivity for a Scalable Error-Corrected Ion-Trap Quantum Processor Architecture
author Valentini, M.
author_facet Valentini, M.
Van Mourik, M.W.
Butt, F.
Wahl, J.
Dietl, M.
Pfeifer, M.
Anmasser, F.
Colombe, Y.
Rössler, C.
Holz, P.C.
Blatt, R.
Bermudez, A.
Müller, M.
Monz, T.
Schindler, P.
author_role author
author2 Van Mourik, M.W.
Butt, F.
Wahl, J.
Dietl, M.
Pfeifer, M.
Anmasser, F.
Colombe, Y.
Rössler, C.
Holz, P.C.
Blatt, R.
Bermudez, A.
Müller, M.
Monz, T.
Schindler, P.
author2_role author
author
author
author
author
author
author
author
author
author
author
author
author
author
topic Architecture
Computer architecture
Error correction
Quantum channel
Quantum electronics
Quantum noise
Qubits
Array architecture
Coupling rate
Ion traps
Large scale quantum computers
Linear strings
Processor architectures
Quantum processors
Trapped ion
Two-dimensional
Two-dimensional lattices
Trapped ions
topic_facet Architecture
Computer architecture
Error correction
Quantum channel
Quantum electronics
Quantum noise
Qubits
Array architecture
Coupling rate
Ion traps
Large scale quantum computers
Linear strings
Processor architectures
Quantum processors
Trapped ion
Two-dimensional
Two-dimensional lattices
Trapped ions
description A major hurdle for building a large-scale quantum computer is increasing the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be achieved by moving subregisters consisting of a few ions across the processor. Here, we focus on an architecture, which we refer to as the quantum spring array (QSA), that is based on a rectangular two-dimensional lattice of linear strings of ions. Connectivity between adjacent ion strings can be controlled by adjusting their separation. This requires control of trapping potentials along two directions, one along the axis of the ion string and one radial to it. In this work, we investigate key elements of the QSA architecture along both directions: We show that the coupling rate between neighboring lattice sites increases with the number of ions per site and the motion of the coupled system can be resilient to electrical noise, both being key requisites for fast and high-fidelity quantum gate operations. The coherence of the coupling is assessed and an entangling gate between qubits stored in radially separated trapping regions is demonstrated. Moreover, we demonstrate control over radio-frequency signals to adjust the radial separation, and thus the coupling rate, between strings. We further present constructions for the implementation of parallelized, transversal gate operations, and map the QSA architecture to code primitives for fault-tolerant quantum error correction, providing a step towards a quantum processor architecture that is optimized for large-scale operation. © 2025 authors. Published by the American Physical Society. Published by the American Physical Society under the terms of the "https://creativecommons.org/licenses/by/4.0/"Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.
publishDate 2025
format article
status_str publishedVersion
url http://hdl.handle.net/10261/427332
https://www.scopus.com/inward/record.uri?eid=2-s2.0-105022605887&doi=10.1103%2Fb9s1-6r44&partnerID=40&md5=c6e2b12aee0dfd56ff0846ff9c731983
eu_rights_str_mv openAccess
publisher American Physical Society
institution Consejo Superior de Investigaciones Científicas (CSIC)
collection DIGITAL.CSIC. Repositorio Institucional del CSIC
reponame_str DIGITAL.CSIC. Repositorio Institucional del CSIC
instname_str Consejo Superior de Investigaciones Científicas (CSIC)
_version_ 1878431152849551360
publishDateSort 2025
author_browse Anmasser, F.
Bermudez, A.
Blatt, R.
Butt, F.
Colombe, Y.
Dietl, M.
Holz, P.C.
Monz, T.
Müller, M.
Pfeifer, M.
Rössler, C.
Schindler, P.
Valentini, M.
Van Mourik, M.W.
Wahl, J.
publisherStr American Physical Society
score 6,924472

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