Mitosis: A speculative multithreaded processor based on pre-computation slices

This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads. Speculative multithreading increases single-threaded application performance by exploiting thread-level parallelism spe...

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Autores: Madriles Gimeno, Carles, García Quiñones, Carlos, Sánchez, Jesús, Marcuello, Pedro, González Colás, Antonio María|||0000-0002-0009-0996, Tullsen, Dean, Wang, Hong, Shen, John P.
Formato: artículo
Fecha de publicación:2008
País:España
Recursos:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/100454
Acesso em linha:https://hdl.handle.net/2117/100454
https://dx.doi.org/10.1109/TPDS.2007.70797
Access Level:acceso abierto
Palavra-chave:Compilers (Computer programs)
Cache memory
Speculative thread-level parallelism
Precomputation slices
Thread partitioning
Multicore architecture
Compiladors (Programes d'ordinador)
Memòria cau
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
id ES_104bd9ee536dc85adf68d3e00a785cc2
oai_identifier_str oai:upcommons.upc.edu:2117/100454
network_acronym_str ES
network_name_str España
spelling Mitosis: A speculative multithreaded processor based on pre-computation slices Madriles Gimeno, Carles García Quiñones, Carlos Sánchez, Jesús Marcuello, Pedro González Colás, Antonio María|||0000-0002-0009-0996 Tullsen, Dean Wang, Hong Shen, John P. Compilers (Computer programs) Cache memory Speculative thread-level parallelism Precomputation slices Thread partitioning Multicore architecture Compiladors (Programes d'ordinador) Memòria cau Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads. Speculative multithreading increases single-threaded application performance by exploiting thread-level parallelism speculatively, that is, executing code in parallel, even when the compiler or runtime system cannot guarantee that the parallelism exists. The proposed approach is based on predicting/computing thread input values via software through a piece of code that is added at the beginning of each thread (the precomputation slice). A precomputation slice is expected to compute the correct thread input values most of the time but not necessarily always. This allows aggressive optimization techniques to be applied to the slice to make it very short. This paper focuses on the microarchitecture that supports this execution model. The primary novelty of the microarchitecture is the hardware support for the execution and validation of precomputation slices. Additionally, this paper presents new architectures for the register file and the cache memory in order to support multiple versions of each variable and allow for efficient rollback in case of misspeculation. We show that the proposed microarchitecture, together with the compiler support, achieves an average speedup of 2.2 for applications that conventional nonspeculative approaches are not able to parallelize at all. Peer Reviewed https://hdl.handle.net/2117/100454 https://dx.doi.org/10.1109/TPDS.2007.70797
title Mitosis: A speculative multithreaded processor based on pre-computation slices
spellingShingle Mitosis: A speculative multithreaded processor based on pre-computation slices
Madriles Gimeno, Carles
Compilers (Computer programs)
Cache memory
Speculative thread-level parallelism
Precomputation slices
Thread partitioning
Multicore architecture
Compiladors (Programes d'ordinador)
Memòria cau
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
title_short Mitosis: A speculative multithreaded processor based on pre-computation slices
title_full Mitosis: A speculative multithreaded processor based on pre-computation slices
title_fullStr Mitosis: A speculative multithreaded processor based on pre-computation slices
title_full_unstemmed Mitosis: A speculative multithreaded processor based on pre-computation slices
title_sort Mitosis: A speculative multithreaded processor based on pre-computation slices
author Madriles Gimeno, Carles
author_facet Madriles Gimeno, Carles
García Quiñones, Carlos
Sánchez, Jesús
Marcuello, Pedro
González Colás, Antonio María|||0000-0002-0009-0996
Tullsen, Dean
Wang, Hong
Shen, John P.
author_role author
author2 García Quiñones, Carlos
Sánchez, Jesús
Marcuello, Pedro
González Colás, Antonio María|||0000-0002-0009-0996
Tullsen, Dean
Wang, Hong
Shen, John P.
author2_role author
author
author
author
author
author
author
topic Compilers (Computer programs)
Cache memory
Speculative thread-level parallelism
Precomputation slices
Thread partitioning
Multicore architecture
Compiladors (Programes d'ordinador)
Memòria cau
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
topic_facet Compilers (Computer programs)
Cache memory
Speculative thread-level parallelism
Precomputation slices
Thread partitioning
Multicore architecture
Compiladors (Programes d'ordinador)
Memòria cau
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
description This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads. Speculative multithreading increases single-threaded application performance by exploiting thread-level parallelism speculatively, that is, executing code in parallel, even when the compiler or runtime system cannot guarantee that the parallelism exists. The proposed approach is based on predicting/computing thread input values via software through a piece of code that is added at the beginning of each thread (the precomputation slice). A precomputation slice is expected to compute the correct thread input values most of the time but not necessarily always. This allows aggressive optimization techniques to be applied to the slice to make it very short. This paper focuses on the microarchitecture that supports this execution model. The primary novelty of the microarchitecture is the hardware support for the execution and validation of precomputation slices. Additionally, this paper presents new architectures for the register file and the cache memory in order to support multiple versions of each variable and allow for efficient rollback in case of misspeculation. We show that the proposed microarchitecture, together with the compiler support, achieves an average speedup of 2.2 for applications that conventional nonspeculative approaches are not able to parallelize at all.
publishDate 2008
format article
url https://hdl.handle.net/2117/100454
https://dx.doi.org/10.1109/TPDS.2007.70797
language eng
eu_rights_str_mv openAccess
institution Universitat Politècnica de Catalunya (UPC)
collection UPCommons. Portal del coneixement obert de la UPC
reponame_str UPCommons. Portal del coneixement obert de la UPC
instname_str Universitat Politècnica de Catalunya (UPC)
_version_ 1878431546205011968
publishDateSort 2008
author_browse García Quiñones, Carlos
González Colás, Antonio María|||0000-0002-0009-0996
Madriles Gimeno, Carles
Marcuello, Pedro
Shen, John P.
Sánchez, Jesús
Tullsen, Dean
Wang, Hong
score 6,924472

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