Explaining dynamic cache partitioning speed ups

Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications th...

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Bibliographic Details
Authors: Moretó Planas, Miquel|||0000-0002-9848-8758, Cazorla, Francisco, Ramírez Bellido, Alejandro, Valero Cortés, Mateo|||0000-0003-2917-2482
Format: article
Publication Date:2007
Country:España
Institution:Universitat Politècnica de Catalunya (UPC)
Repository:UPCommons. Portal del coneixement obert de la UPC
Language:English
OAI Identifier:oai:upcommons.upc.edu:2117/102823
Online Access:https://hdl.handle.net/2117/102823
https://dx.doi.org/10.1109/L-CA.2007.3
Access Level:Open access
Keyword:Microprocessors
Cache memory
Microprocessor chips
Cache storage
Microprocessadors
Memòria cau
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Description
Summary:Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications that are running in the architecture. In this paper, we introduce some metrics that characterize applications and allow us to give a clear and simple model to explain final throughput speed ups.