On-chip interconnects and instruction steering schemes for clustered microarchitectures
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection networks for clustered superscalar microarchitectures. This new class of i...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2005 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/100490 |
| Acceso en línea: | https://hdl.handle.net/2117/100490 https://dx.doi.org/10.1109/TPDS.2005.23 |
| Access Level: | acceso abierto |
| Palabra clave: | Multiprocessors Logic design Clustered microarchitecture Intercluster communication On-chip interconnects Instruction steering Complexity Multiprocessadors Estructura lògica Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection networks for clustered superscalar microarchitectures. This new class of interconnects has demands and characteristics different from traditional multiprocessor networks. In particular, in a clustered microarchitecture, a low intercluster communication latency is essential for high performance. We propose some point-to-point cluster interconnects and new improved instruction steering schemes. The results show that these point-to-point interconnects achieve much better performance than bus-based ones, and that the connectivity of the network together with effective steering schemes are key for high performance. We also show that these interconnects can be built with simple hardware and achieve a performance close to that of an idealized contention-free model. |
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